1. Field of the Invention
The invention relates to the technique field of trace and debug and, more particularly, to a low-cost trace and debug method and system for a processor.
2. Description of Related Art
With the rapid development of electronic technologies, various processor architectures have accordingly become more complex. Thus, a processor typically has an internal hardware debug module to enable a designer to easily use the processor in developing new systems. FIG. 1 is a block diagram of an internal hardware debug module of a processor. As shown in FIG. 1, a trace monitor 130 monitors the signals on the address bus and the data bus, and stores the signals in a trace buffer 140 for further analysis by the designer. However, such an architecture is suitable for only a processor core without a cache function.
To overcome the aforementioned problem, a MIPS processor uses its embedded circuit to send the variations of a program counter (PC) to an integrated development environment (IDE) software through additional EJTAG (Enhanced Joint Test Action Group) pins. Then, the MIPS processor's internal status can be reconstructed in the IDE software. However, when the quantity of EJTAG pins is not sufficient, the corresponding output information is very little. To parse the little information of the MIPS processor, the IDE software will become quite complicated. In order to simplify the complexity of the IDE software, the MIPS processor needs to be halted until the information is output to the IDE software completely. As such, a real-time PC trace is difficult and the MIPS processor cannot take a data trace.
FIG. 2 is a block diagram of an internal hardware debug module of a typical ARM processor, which uses an embedded trace device to output the traced information of the ARM processor core to an IDE software through its debug pins. Such a way can obtain a real-time trace, but the embedded trace device needs about 17K to 55K gates and additional output pins, which increases the hardware cost. In addition, for a high-speed ARM processor or the limited additional output pins, larger embedded trace buffer is required to have the PC or data trace function.
A typical SH5 processor is built with a debug link and a JTAG interface. In addition, traced information is stored in a DM FIFO (debug module first in first out). The DM FIFO is a 3*64-bit FIFO. Such a way can use less memory, but when the FIFO is filled with data, the processor needs to be halted and new traced data is discarded. The FIFO can be set as a circular FIFO. When the circular FIFO is filled with data, the processor does not need to be halted but new traced data will cover old traced data. Therefore, it is desirable to provide an improved trace and debug method and system to mitigate and/or obviate the aforementioned problems.